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?2010 fairchild semiconductor corporation fdd20an06a0_f085 rev. b1 fdd20an06a0 f085 fdd20an06a0 f085 _ n-channel powertrench ? mosfet 60v, 45a, 20m features ? r ds(on) = 17m (typ.), v gs = 10v, i d = 45a ? q g (tot) = 15nc (typ.), v gs = 10v ? low miller charge ? low q rr body diode ? uis capability (single pulse and repetitive pulse) ? qualified to aec q101 formerly developmental type 82547 applications ? motor / body load control ? abs systems ? powertrain management ? injection systems ? dc-dc converters and off-line ups ? distributed power architectures and vrms ? primary switch for 12v and 24v systems mosfet maximum ratings t c = 25c unless otherwise noted thermal characteristics this product has been designed to meet the extreme test conditions and environment demanded by the aut omotive industry. for a copy of the requirements, see aec q101 at: http://w ww.aecouncil.com/ reliability data can be found at: http://www.fairch ildsemi.com/products/discrete/reliability/index.htm l. all fairchild semiconductor products are manufactur ed, assembled and tested under iso9000 and qs9000 q uality systems certification. symbol parameter ratings units v dss drain to source voltage 60 v v gs gate to source voltage 20 v i d drain current 45 a continuous (t c = 25 o c, v gs = 10v) continuous (t c = 100 o c, v gs = 10v) 32 a continuous (t amb = 25 o c, v gs = 10v, r ja = 52 o c/w) 8 a pulsed figure 4 a e as single pulse avalanche energy ( note 1) 50 mj p d power dissipation 90 w derate above 25 o c 0.60 w/ o c t j , t stg operating and storage temperature -55 to 175 o c r jc thermal resistance junction to case to-252 1.67 o c/w r ja thermal resistance junction to ambient to-252 100 o c/w r ja thermal resistance junction to ambient to-252, 1in 2 copper pad area 52 o c/w d g s to-252aa fdd series gate source (flange) drain _ n-channel powertrench ? mosfet may 20 10 l e a d f r e e m t a e l n t i o m p e n i ? rohs compliant
package marking and ordering information electrical characteristics t c = 25c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics (v gs = 10v) drain-source diode characteristics notes: 1: starting t j = 25c, l = 80 h, i as = 36a. device marking device package reel size tape width quant ity 16mm 2500 units symbol parameter test conditions min typ max units b vdss drain to source breakdown voltage i d = 250 a, v gs = 0v 60 - - v i dss zero gate voltage drain current v ds = 50v - - 1 a v gs = 0v t c = 150 o c - - 250 i gss gate to source leakage current v gs = 20v - - 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 2 - 4 v r ds(on) drain to source on resistance i d = 45a, v gs = 10v - 0.017 0.020 i d = 45a, v gs = 10v, t j = 175 o c - 0.039 0.047 c iss input capacitance v ds = 25v, v gs = 0v, f = 1mhz - 950 - pf c oss output capacitance - 185 - pf c rss reverse transfer capacitance - 60 - pf q g(tot) total gate charge at 10v v gs = 0v to 10v v dd = 30v i d = 45a i g = 1.0ma 15 19 nc q g(th) threshold gate charge v gs = 0v to 2v - 2 2.6 nc q gs gate to source gate charge - 6 - nc q gs2 gate charge threshold to plateau - 4 - nc q gd gate to drain miller charge - 4.5 - nc t on turn-on time v dd = 30v, i d = 45a v gs = 10v, r gs = 20 - - 164 ns t d(on) turn-on delay time - 11 - ns t r rise time - 98 - ns t d(off) turn-off delay time - 23 - ns t f fall time - 33 - ns t off turn-off time - - 84 ns v sd source to drain diode voltage i sd = 45a - - 1.25 v i sd = 22a - - 1.0 v t rr reverse recovery time i sd = 45a, di sd /dt = 100a/ s - - 32 ns q rr reverse recovered charge i sd = 45a, di sd /dt = 100a/ s - - 25 nc fdd20an06a0 f085 _ n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation fdd20an06a0_f085 rev. b1 fdd20an06a0 fdd20an06a0_f085 to-252aa 330mm
typical characteristics t c = 25c unless otherwise noted figure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal imp edance figure 4. peak current capability t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 175 0.2 0.4 0.6 0.8 1.0 1.2 125 150 0 10 20 30 40 50 25 50 75 100 125 150 175 i d , drain current (a) t c , case temperature ( o c) 0.1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 2 t , rectangular pulse duration (s) z jc , normalized thermal impedance notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 0.5 0.2 0.1 0.05 0.01 0.02 duty cycle - descending order single pulse 100 600 40 i dm , peak current (a) t, pulse width (s) 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: transconductance may limit current in this region v gs = 10v fdd20an06a0 f085 _ n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation fdd20an06a0_f085 rev. b1
figure 5. forward bias safe operating area note: refer to fairchild application notes an7514 a nd an7515 figure 6. unclamped inductive switching capability figure 7. transfer characteristics figure 8. satur ation characteristics figure 9. drain to source on resistance vs drain current figure 10. normalized drain to source on resistance vs junction temperature typical characteristics t c = 25c unless otherwise noted 0.1 1 10 100 1000 1 10 100 v ds , drain to source voltage (v) i d , drain current (a) t j = max rated t c = 25 o c single pulse limited by r ds(on) area may be operation in this 10 s 1ms dc 100 s 10ms 1 10 100 0.1 1 10 300 0.01 i as , avalanche current (a) t av , time in avalanche (ms) starting t j = 25 o c starting t j = 150 o c t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] 0 20 40 60 80 100 4 5 6 7 8 9 i d , drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = 175 o c t j = 25 o c t j = -55 o c 0 20 40 60 80 100 0 1 2 3 i d , drain current (a) v ds , drain to source voltage (v) v gs = 5v v gs = 20v v gs = 7v pulse duration = 80 s duty cycle = 0.5% max t c = 25 o c v gs = 10v v gs = 6v 15.5 16.0 16.5 17.0 17.5 0 10 20 30 40 50 i d , drain current (a) v gs = 10v drain to source on resistance(m ) pulse duration = 80 s duty cycle = 0.5% max 0.5 1.0 1.5 2.0 2.5 -80 -40 0 40 80 120 160 200 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d = 45a pulse duration = 80 s duty cycle = 0.5% max fdd20an06a0 f085 _ n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation fdd20an06a0_f085 rev. b1
figure 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacitance vs drain to source voltage figure 14. gate charge waveforms for constant gate current typical characteristics t c = 25c unless otherwise noted 0.4 0.6 0.8 1.0 1.2 -80 -40 0 40 80 120 160 200 v gs = v ds , i d = 250 a normalized gate t j , junction temperature ( o c) threshold voltage 0.90 0.95 1.00 1.05 1.10 1.15 -80 -40 0 40 80 120 160 200 t j , junction temperature ( o c) normalized drain to source i d = 250 a breakdown voltage 100 1000 0.1 1 10 40 2000 60 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd 0 2 4 6 8 10 0 3 6 9 12 15 v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 30v i d = 45a i d = 9a waveforms in descending order: fdd20an06a0 f085 _ n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation fdd20an06a0_f085 rev. b1
test circuits and waveforms figure 15. unclamped energy test circuit figure 16. unclamped energy waveforms figure 17. gate charge test circuit figure 18. gat e charge waveforms figure 19. switching time test circuit figure 20. switching time waveforms t p v gs 0.01 l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 v gs + - v ds v dd dut i g(ref) l v dd q g(th) v gs = 2v q gs2 q g(tot) v gs = 10v v ds v gs i g(ref) 00 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 00 fdd20an06a0 f085 _ n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation fdd20an06a0_f085 rev. b1
thermal resistance vs. mounting pad area the maximum rated junction temperature, t jm , and the thermal resistance of the heat dissipating path det ermines the maximum allowable device power dissipation, p dm , in an application. therefore the applications ambient temperature, t a ( o c), and thermal resistance r ja ( o c/w) must be reviewed to ensure that t jm is never exceeded. equation 1 mathematically represents the relationship a nd serves as the basis for establishing the rating of the part. in using surface mount devices such as the to-252 package, the environment in which it is applied wil l have a significant influence on the parts current and max imum power dissipation ratings. precise determination of p dm is complex and influenced by many factors: 1. mounting pad area onto which the device is attac hed and whether there is copper on one side or both sides o f the board. 2. the number of copper layers and the thickness of the board. 3. the use of external heat sinks. 4. the use of thermal vias. 5. air flow and board orientation. 6. for non steady state applications, the pulse wid th, the duty cycle and the transient thermal response of th e part, the board and the environment they are in. fairchild provides thermal information to assist th e designers preliminary application evaluation. figu re 21 defines the r ja for the device as a function of the top copper (component side) area. this is for a horizon tally positioned fr-4 board with 1oz copper after 1000 se conds of steady state power with no air flow. this graph provides the necessary information for calculation of the st eady state junction temperature or power dissipation. pulse applications can be evaluated using the fairchild d evice spice thermal model or manually utilizing the norma lized maximum transient thermal impedance curve. thermal resistances corresponding to other copper a reas can be obtained from figure 21 or by calculation using equation 2 or 3. equation 2 is used for copper area defined in inches square and equation 3 is for area in centim eters square. the area, in square inches or square centim eters is the top copper area including the gate and source p ads. (eq. 1) p d m t jm t a C ( ) r ja ----------------------------- = area in inches squared (eq. 2) r ja 33.32 23.84 0.268 area + ( ) ------------------------------------- + = (eq. 3) r ja 33.32 154 1.73 area + ( ) ---------------------------------- + = area in centimeters squared 25 50 75 100 125 0.01 0.1 1 10 figure 21. thermal resistance vs mounting pad area r ja = 33.32+ 23.84/(0.268+area) eq.2 r ja ( o c/w) area, top copper area in 2 (cm 2 ) r ja = 33.32+ 154/(1.73+area) eq.3 (0.645) (6.45) (64.5) (0.0645) fdd20an06a0 f085 _ n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation fdd20an06a0_f085 rev. b1
pspice electrical model .subckt fdd20an06a0 2 1 3 ; rev april 2003 ca 12 8 4.4e-10 cb 15 14 4.4e-10 cin 6 8 9.2e-10 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 67.2 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 lgate 1 9 5e-9 ldrain 2 5 1.0e-9 lsource 3 7 2e-9 rlgate 1 9 50 rldrain 2 5 10 rlsource 3 7 20 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 1e-3 rgate 9 20 4.7 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 10e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5, 51)/(1e-6*150),2.7))} .model dbodymod d (is=3.8e-12 n=1.06 rs=4e-3 trs1=2 .4e-3 trs2=1.1e-6 + cjo=6.8e-10 m=0.53 tt=2.3e-8 xti=3.9) .model dbreakmod d (rs=1.8 trs1=1e-3 trs2=-8.9e-6) .model dplcapmod d (cjo=2.7e-10 is=1e-30 n=10 m=0.4 4) .model mmedmod nmos (vto=3.8 kp=2 is=1e-30 n=10 tox =1 l=1u w=1u rg=4.7 t_abs=25) .model mstromod nmos (vto=4.34 kp=35 is=1e-30 n=10 tox=1 l=1u w=1u t_abs=25) .model mweakmod nmos (vto=3.27 kp=0.03 is=1e-30 n=1 0 tox=1 l=1u w=1u rg=47 rs=0.1 t_abs=25) .model rbreakmod res (tc1=9e-4 tc2=1e-7) .model rdrainmod res (tc1=6e-3 tc2=8e-5) .model rslcmod res (tc1=1e-3 tc2=3.5e-5) .model rsourcemod res (tc1=9e-3 tc2=1e-6) .model rvthresmod res (tc1=-5.1e-3 tc2=-1.3e-5) .model rvtempmod res (tc1=-3e-3 tc2=1e-7) .model s1amod vswitch (ron=1e-5 roff=0.1 von=-8 vof f=-5) .model s1bmod vswitch (ron=1e-5 roff=0.1 von=-5 vof f=-8) .model s2amod vswitch (ron=1e-5 roff=0.1 von=-2 vof f=-1.5) .model s2bmod vswitch (ron=1e-5 roff=0.1 von=-1.5 v off=-2) .ends note: for further discussion of the pspice model, c onsult a new pspice sub-circuit for the power mosfet featu ring global temperature options ; ieee power electronics specialist conference reco rds, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 68 + - 5 51 + - 19 8 + - 17 18 68 + - 58 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 fdd20an06a0 f085 _ n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation fdd20an06a0_f085 rev. b1
saber electrical model rev april 2003 template fdd20an06a0 n2,n1,n3 =m_temp electrical n2,n1,n3 number m_temp=25 { var i iscl dp..model dbodymod = (isl=3.8e-12,nl=1.06,rs=4e-3, trs1=2.4e-3,trs2=1.1e-6,cjo=6.8e-10,m=0.53,tt=2.3e- 8,xti=3.9) dp..model dbreakmod = (rs=1.8,trs1=1e-3,trs2=-8.9e- 6) dp..model dplcapmod = (cjo=2.7e-10,isl=10e-30,nl=1 0,m=0.44) m..model mmedmod = (type=_n,vto=3.8,kp=2,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.34,kp=35,is=1e -30, tox=1) m..model mweakmod = (type=_n,vto=3.27,kp=0.03,is=1e -30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8, voff=-5) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-5, voff=-8) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2, voff=-1.5) sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1. 5,voff=-2) c.ca n12 n8 = 4.4e-10 c.cb n15 n14 = 4.4e-10 c.cin n6 n8 = 9.2e-10 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 67.2 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 5e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2e-9 res.rlgate n1 n9 = 50 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 20 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, te mp=m_temp m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w= 1u ,temp=m_temp m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u ,temp=m_temp res.rbreak n17 n18 = 1, tc1=9e-4,tc2=1e-7 res.rdrain n50 n16 = 1e-3, tc1=6e-3,tc2=8e-5 res.rgate n9 n20 = 4.7 res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=3.5e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 10e-3, tc1=9e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-5.1e-3,tc2=-1.3e-5 res.rvtemp n18 n19 = 1, tc1=-3e-3,tc2=1e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51)) ))*((abs(v(n5,n51)*1e6/150))** 2.7)) }} 18 22 + - 68 + - 19 8 + - 17 18 68 + - 58 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 fdd20an06a0 f085 _ n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation fdd20an06a0_f085 rev. b1
pspice thermal model rev 23 april 2003 fdd20an06a0t ctherm1 th 6 1.8e-3 ctherm2 6 5 8.0e-3 ctherm3 5 4 9.0e-3 ctherm4 4 3 1.1e-2 ctherm5 3 2 1.2e-2 ctherm6 2 tl 2.0e-2 rtherm1 th 6 3.0e-2 rtherm2 6 5 1.0e-1 rtherm3 5 4 1.4e-1 rtherm4 4 3 2.3e-1 rtherm5 3 2 4.1e-1 rtherm6 2 tl 4.2e-1 saber thermal model saber thermal model fdd20an06a0t template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =1.8e-3 ctherm.ctherm2 6 5 =8.0e-3 ctherm.ctherm3 5 4 =9.0e-3 ctherm.ctherm4 4 3 =1.1e-2 ctherm.ctherm5 3 2 =1.2e-2 ctherm.ctherm6 2 tl =2.0e-2 rtherm.rtherm1 th 6 =3.0e-2 rtherm.rtherm2 6 5 =1.0e-1 rtherm.rtherm3 5 4 =1.4e-1 rtherm.rtherm4 4 3 =2.3e-1 rtherm.rtherm5 3 2 =4.1e-1 rtherm.rtherm6 2 tl =4.2e-1 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case fdd20an06a0 f085 _ n-channel powertrench ? mosfet ?2010 fairchild semiconductor corporation fdd20an06a0_f085 rev. b1
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